ics1726-11 mds 1726-11 a 1 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com low emi clock generator preliminary information description the ics1726-11 generates a low emi output clock from a clock or crystal input. the part is designed to dither the lcd interface clock for pdas, printers, scanners, modems, copiers, and others. using ics? proprietary mix of analog and digital phase-locked loop (pll) technology, the device spreads the frequency spectrum of the output, reducing the frequency amplitude peaks by several db. the ics1726-11 offers both centered and down spread from a high-speed clock input. ics offers many other clocks for computers and computer peripherals. consult us when you need to remove crystals and oscillators from your board. features ? packaged in 8-pin soic/tssop ? provides a spread spectrum output clock ? supports flat panel controllers ? accepts a clock or crystal input (provides same frequency dithered output) ? input frequency range of 16 to 32 mhz ? output frequency range of 16 to 32 mhz ? center and down spread ? peak reduction by 8 db to 16 db typical on 3rd through 19th odd harmonics ? low emi feature can be disabled ? includes power down ? operating voltage of 3.3 v ? advanced, low-power cmos process block diagram pll clock synthesis and spread spectrum circuitry x1 s1:0 ssclk 2 gnd vdd clock buffer/ crystal ocsillator x1/clk x2 external caps required for with crystal for accurate tuning of the clock
low emi clock generator mds 1726-11 a 2 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics1726-11 preliminary information pin assignment spread direction and percentage select table 0 = connect to gnd m = unconnected (floating) 1 = connect directly to vdd pin descriptions x1/iclk gnd s1 vdd s0 nc ssclk x2 1 2 3 4 8 7 6 5 8 pin (150 mil) soic 8-pin (173 mil) tssop s1 pin 3 s0 pin 4 spread direction spread percentage 0 0 center 1.4 0 m center 1.1 0 1 center 0.6 m 0 center 0.5 mmno spread - m 1 down -1.6 1 0 down -2.0 1 m down -0.7 1 1 down -3.0 pin number pin name pin type pin description 1 x1/iclk input connect to a 16 to 32 mhz crystal or clock. 2 gnd power connect to ground. 3 s1 input function select 1 input. selects spread amount and direction per table above. (default-internal mid-level). 4 s0 input function select 0 input. selects spread amount and direction per table above. (default-internal mid-level). 5 ssclk output clock output with spread spectrum. 6 nc ? no connect. do not connect this pin to anything. 7 vdd power connect to +3.3 v. 8 x2 xo crystal connection to a 16 to 32 mhz crystal. leave unconnected for clock.
low emi clock generator mds 1726-11 a 3 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics1726-11 preliminary information external components the ics1726-11 requires a minimum number of external components for proper operation. decoupling capacitor a decoupling capacitor of 0.01f must be connected between vdd and gnd on pins 7 and 2, as close to these pins as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock output and the load is over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . tri-level select pin operation the s1, s0 select pins are tri-level, meaning they have three separate states to ma ke the selections shown in the table on page 2. to select the m (mid) level, the connection to these pins must be eliminated by either floating them, or tri-stating the driver connected to the select pin. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between the decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) to minimize emi, the 33 ? series termination resistor (if needed) should be placed close to the clock output. 3) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the ics1726-11. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. crystal information the crystal used should be a fundamental mode (do not use third overtone), parallel resonant. crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value of these capacitors is given by the following equation: crystal caps (pf) = (c l - 6) x 2 in the equation, c l is the crystal load capacitance. so, for a crystal with a 16 pf load capacitance, two 20 pf [(16-6) x 2] capacitors should be used. spread spectrum profile the ics1726-11 low emi clock generator uses an optimized frequency slew rate to facilitate down stream tracking by zero delay buffers and other pll devices. the frequency modulation amplitude is constant despite variations of the input frequency. time frequency modulation rate
low emi clock generator mds 1726-11 a 4 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics1726-11 preliminary information absolute maximum ratings stresses above the ratings listed below can cause pe rmanent damage to the ics1726-11. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v , ambient temperature 0 to +70 c item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.0 3.6 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.3 3.6 v supply current idd no load, at 3.3 v, fin=24 mhz 23 30 ma no load, at 3.3 v, fin=32 mhz 35 ma input high voltage v ih 0.85vdd vdd vdd v input middle voltage v ihm 0.4vdd 0.5vdd 0.6vdd v input low voltage v il 0.0 0.0 0.15vdd v output high voltage v oh cmos, i oh = -4 ma 2.4 v output high voltage v oh i oh = -6 ma 2.0 v output low voltage v ol i ol = -4 ma 0.4 v i ol = -10 ma 1.2 v input capacitance c in1 s0, s1, pins 4 6 pf c in2 x1, x2 pins 6 9 pf
low emi clock generator mds 1726-11 a 5 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics1726-11 preliminary information ac electrical characteristics unless stated otherwise, vdd = 3.3 v , ambient temperature 0 to +70 c thermal characteristics parameter symbol conditions min. typ. max. units input clock frequency 16 32 mhz output clock frequency 16 32 mhz input clock duty cycle time above vdd/2 40 60 % output clock duty cycle time above 1.5 v 45 50 55 % cycle to cycle jitter fin=27 mhz, fout=27 mhz 200 450 ps output rise time t r 0.4 to 2.4 v 2.4 3.2 4.0 ns output fall time t f 2.4 to 0.4 v 2.4 3.2 4.0 ns emi peak frequency reduction 8 to 16 db parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w
low emi clock generator mds 1726-11 a 6 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics1726-11 preliminary information package outline and package dimensions (8-pin tssop) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 2.90 3.10 0.114 0.122 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa - 0.10 - 0.004
low emi clock generator mds 1726-11 a 7 revision 092905 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics1726-11 preliminary information package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics1726g-11 26G11 tubes 8-pin tssop 0 to +70 c ics1726g-11t 26G11 tape and reel 8-pin tssop 0 to +70 c ics1726g-11lf 26G11l tubes 8-pin tssop 0 to +70 c ics1726g-11lft 26G11l tape and reel 8-pin tssop 0 to +70 c ics1726m-11 1726m11 tubes 8-pin soic 0 to +70 c ics1726m-11t 1726m11 tape and reel 8-pin soic 0 to +70 c ics1726m-11lf 1726m11l tubes 8-pin soic 0 to +70 c ics1726m-11lft 1726m11l tape and reel 8-pin soic 0 to +70 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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